1. Field of the Invention
The present invention relates to the technical field of static random access memories and, more particularly, to a static random access memory with ripple bit lines or search lines for improving nanometer-level current leakage and variation tolerance as well as density and performance.
2. Description of Related Art
With advanced semiconductor processes, such as a process of lower than 100 nm, it has a sufficient potential to carry out a low voltage, low power, and low density static random access memory (SRAM). However, the variations of the process, applied voltage and temperature can impact on the advanced semiconductor process. The variations can reduce the stability of the SRAM. For example, a read-disturb of the SRAM can reduce the read static noise margin (RSNM) and thus negatively influence the reading stability.
FIG. 1 is a schematic diagram of a typical static random access memory. As shown in FIG. 1, the SRAM includes a cell column array with a plurality of rows, each having a plurality of cells connected to another word line. The voltage of each word line is controlled by a word line driver corresponding to the word line. Each cell is implemented with a latch and at least one gate turn-on transistor. The latch is formed of a pair of cross-coupled inverters, and has two storage nodes. The transistor has a control terminal (e.g., gate) connected to the word line, and two channel terminals (e.g., source and drain) connected to one of the two storage nodes and a corresponding bit line respectively.
For reading a cell column array and a cell on the cell column array, the bit line (VBL, VBL) of the transistor is pre-charged to a high voltage with logic 1. The word line (VWL) of the cell column array and the transistor of the cell are enabled by the word line driver to thereby turn on the storage node to the bit line (VBL, VBL). If the storage node stores a low voltage with logic 0, the latch of the cell discharges the pre-charged high voltage to the low voltage with logic 0.
The SRAM has a higher and higher density as the bit line (VBL, VBL) connects more and more cells. In this case, the current leakage is accordingly increased more and more. Namely, the data pre-charged in the selected bit line can be influenced easily by the leakage of other cells, resulting in reducing the sense margin.
To overcome this, the article “IBM POWER6 SRAM arrays” issued by D. W. Plass and Y. H. Chan in IBM J. Res. & Dev. Vol. 51, No. 6, November 2007, pp. 747-756 has proposed a bit line (BL) without connecting excessive SRAM cells in order to avoid read disturbance and large bit line leakage, and the shorter local bit lines (LBLs) are operated with a global bit line (GBL), as shown in FIG. 2. Since the shorter LBLs are used, the advantages of better sense margin, less read disturbance, and improved process variation and current leakage tolerance are obtained. However, when an LBL is connected to the GBL through a multiplexer, it increases the chip area, and an additional metal layer is required for the GBL.
The article “A 0.7V Single-Supply SRAM with 0.495 μm2 cell in 65 nm technology utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme” issued by K. Kushida et al. in Symp. VLSI Circuits, 2008, pp. 46-47 has proposed the transistors CSL_d0 and CSL_u0 to separate one from another LBL to thereby obtain the advantages of better sense margin, process variance, and current leakage without adding the metal layer for the GBL, as shown in FIG. 3. However, a local sensing amplifier is required and added between the transistors CSL_d0, CSL_u0, and accurately controlling the transistors CSL_d0, CSL_u0 to be on/off is required, which causes a more complicated gate control logic circuitry and an accessing speed limit to the SRAM.
The article “Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs” issued by K. Takeda, et al. in Symp. VLSI Circuits, 2010, pp. 101-102 has proposed an agent cell replacing the local sensing amplifier for insulating the LBLs and obtaining the advantages of better sense margin, process variance, and leakage tolerance, as shown in FIG. 4. However, the metal layer is required for the GBL, and the required GBL is too long, which reduces the performance and increases the power consumption.
Therefore, it is desirable to provide an improved SRAM to mitigate and/or obviate the aforementioned problems.